Semiconductor structure and manufacturing method thereof

ABSTRACT

A method of manufacturing a semiconductor structure includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar arid a third conductive pillar are disposed over the substrate. The first conductive pillar comprises a first height, the second conductive pillar comprises a second height, and the third conductive pillar comprises a third height. A first die is disposed over the first conductive pillar. A second die is disposed over the second conductive pillar. A first surface of the first die and a second surface of the second die are at substantially same level.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 17/039,586 filed on Sep. 30, 2020, entitled of “SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF”, which is a divisional application of U.S. patent application Ser. No. 15/863,744 filed on Jan. 5, 2018, entitled of “SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF”, which is a divisional application of U.S. patent application Ser. No. 15/183,131 filed Jun. 15, 2016, the entire contents of all of which are hereby incorporated by reference.

BACKGROUND

Electronic equipments using semiconductor devices are essential for many modern applications. With the advancement of electronic technology, the semiconductor devices are becoming increasingly smaller in size while having greater functionality and greater amounts of integrated circuitry. Due to the miniaturized scale of the semiconductor device, a wafer level packaging (WLP) is widely used for its low cost and relatively simple manufacturing operations. During the WLP operation, a number of semiconductor components are assembled on the semiconductor device. Furthermore, numerous manufacturing operations are implemented within such a small semiconductor device.

However, the manufacturing operations of the semiconductor device involve many steps and operations on such a small and thin semiconductor device. The manufacturing of the semiconductor device in a miniaturized scale becomes more complicated. An increase in a complexity of manufacturing the semiconductor device may cause deficiencies such as poor electrical interconnection, development of cracks, delamination of components or other issues, resulting in a high yield loss of the semiconductor device. The semiconductor device is produced in an undesired configuration, which would further exacerbate materials wastage and thus increase the manufacturing cost.

The semiconductor device is assembled with numbers of integrated components. Since more different components are involved, a complexity of the manufacturing operations of the semiconductor device is increased. There are more challenges to modify a structure of the semiconductor device and improve the manufacturing operations. As such, there is a continuous need to improve the manufacturing the semiconductor and solve the above deficiencies.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic cross sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure.

FIG. 2 is a top cross sectional view of the semiconductor structure of FIG. 1.

FIG. 3 is a schematic cross sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure.

FIG. 4 is a schematic cross sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure.

FIG. 5 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.

FIGS. 5A-5N are schematic views of manufacturing a semiconductor structure by a method of FIG. 5 in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A semiconductor structure is manufactured by a number of operations. During the manufacturing, several dies are disposed over and electrically connected with a substrate to form a package. The dies are bonded over the substrate by several connectors such as bumps, solder joints, etc. However, since coefficient of thermal expansion (CTE) of the substrate and the dies are different from each other, the substrate and the dies would be expanded in different degrees during reflow of the connectors, and resulting in warpage of the package and poor electrical connection between the dies and the substrate (for example, cold joint issue that some of the connectors fail to attach the dies to the substrate and displace away from the substrate).

Furthermore, the dies are encapsulated by molding compound after the reflow. Since the dies may have different thickness from each other, some of backsides of the dies with smaller thickness are covered by the molding compound while some of backsides of the dies with greater thickness are exposed from the molding compound. The thickness difference of the dies would also result in warpage of the package and the poor electrical connection between the dies and the substrate.

In the present disclosure, a semiconductor structure is disclosed. The semiconductor structure includes a substrate, a redistribution layer (RDL) disposed over the substrate, several conductive pillars disposed over the RDL, several dies electrically connected with the substrate by the conductive pillars, and a molding surrounding the dies. The dies are in various thicknesses, and the conductive pillars are in various heights correspondingly. As such, the thickness difference of the dies would be compensated by the conductive pillars in different heights, and the backsides of the dies would be disposed at a level same as each other and would be exposed from the molding. Since no molding is present over the backsides of the dies, the warpage of the semiconductor structure after thermal operations such as reflow would be prevented or minimized, and the electrical connection between the dies and the substrate would be improved. A reliability and performance of the semiconductor structure is improved.

FIG. 1 is a schematic cross sectional view of a semiconductor structure 100 in accordance with various embodiments of the present disclosure. FIG. 2 is a top view of the semiconductor structure 100 of FIG. FIG. 1 shows the cross sectional view of the semiconductor structure 100 along AA′ in FIG. 2. In some embodiments, the semiconductor structure 100 includes a substrate 101, a redistribution layer (RDL) 102, several conductive pillars 103, a first die 104 and a second die (105 or 106). In some embodiments, the semiconductor structure 100 includes several dies (111 or 112). In some embodiments, the semiconductor structure 100 is a semiconductor package. In some embodiments, the semiconductor structure 100 is a multiple dimensional package such as 2.5 dimensional package.

In some embodiments, the substrate 101 is fabricated with a predetermined functional circuit thereon. In some embodiments, the substrate 101 includes several conductive lines and several electrical components such as transistor, diode, etc. connected by the conductive lines. In some embodiments, the substrate 101 is a semiconductive substrate. In some embodiments, the substrate 101 is an interposer or a wafer. In some embodiments, the substrate 101 is a silicon substrate or silicon wafer. In some embodiments, the substrate 101 includes semiconductive material such as silicon, germanium, gallium, arsenic, and combinations thereof. In some embodiments, the substrate 101 includes material such as ceramic, glass, organic, etc. In some embodiments, the substrate 101 is a glass substrate or glass wafer. In some embodiments, the substrate 101 is in a quadrilateral, rectangular, square, polygonal or any other suitable shapes.

In some embodiments, the substrate 101 includes a first surface 101 a and a second surface 101 b opposite to the first surface 101 a. In some embodiments, the first surface 101 a is a front side or an active side that the circuits are disposed thereon. In some embodiments, the second surface 101 b is a back side or an inactive side.

In some embodiments, the RDL 102 is disposed over the substrate 101. In some embodiments, the RDL 102 is disposed over the first surface 101 a of the substrate 101. In some embodiments, the RDL 102 is electrically connected with the substrate 101. In some embodiments, the RDL 102 re-routes paths from the substrate 101 to redistribute I/O terminals of the substrate 101. In some embodiments, the RDL 102 includes a dielectric layer 102 a and several conductive members 102 b. In some embodiments, the dielectric layer 102 a is disposed over the substrate 101. In some embodiments, the dielectric layer 102 a is disposed over the first surface 101 a of the substrate 101. In some embodiments, the dielectric layer 102 a includes several layers of dielectric material stacking over each other. In some embodiments, the dielectric layer 102 a includes dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or the like.

In some embodiments, the conductive members 102 b are disposed over the substrate 101 and surrounded by the dielectric layer 102 a. In some embodiments, the conductive members 102 b are extended through the dielectric layer 102 a. In some embodiments, the conductive members 102 b is configured to electrically connect the circuitry of the substrate 101 with a circuitry external to the substrate 101. In some embodiments, each of the conductive members 102 b includes gold, silver, copper, nickel, tungsten, aluminum, titanium, palladium and/or alloys thereof.

In some embodiments, the conductive member 102 b includes a pad portion 102 b-1, a via portion 102 b-2 and an extending portion 102 b-3. In some embodiments, the extending portion 102 b-3 is disposed over the first surface 101 a of the substrate 101 and configured to electrically connect with the circuitry of the substrate 101. In some embodiments, the via portion 102 b-2 is disposed over the extending portion 102 b-3 and extended through a portion of the dielectric layer 102 a towards the extending portion 102 b-3.

In some embodiments, the pad portion 102 b-1 is disposed over and coupled with the via portion 102 b-2. In some embodiments, the pad portion 102 b-1 is electrically connected with the extending portion 102 b-3 through the via portion 102 b-2. In some embodiments, the pad portion 102 b-1 is electrically connected with the substrate 101 through the extending portion 102 b-3 and the via portion 102 b-2. In some embodiments, a portion of the pad portion 102 b-1 is exposed from the dielectric layer 102 a and is configured to receive a conductive structure subsequently disposed. In some embodiments, a seed layer is disposed over the pad portion 102 b-1 exposed from the dielectric layer 102 a. In some embodiments, the seed layer includes gold, silver, copper, nickel, tungsten, aluminum, titanium, palladium and/or alloys thereof.

In some embodiments, several conductive pillars 103 are disposed over and electrically connected with the conductive members 102 b respectively. In some embodiments, each of the conductive pillars 103 is extended from the corresponding conductive member 102 b. In some embodiments, the conductive pillar 103 includes conductive material such as copper, gold, aluminum, etc. In some embodiments, the conductive pillar 103 is in a cylindrical shape. In some embodiments, a top cross section (a cross section from the top view of the semiconductor structure 100) of the conductive pillar 103 is in various shapes such as circular shape, quadrilateral shape or polygonal shape. In some embodiments, the conductive member 102 b or the pad portion 102 b-1 is configured to receive the conductive pillar 103. In some embodiments, the conductive pillars 103 have various heights. The heights of the conductive pillars 103 are different from each other.

In some embodiments, the conductive pillars 103 include a first conductive pillar 103 a and a second conductive pillar 103 b. In some embodiments, the first conductive pillar 103 a is disposed over and electrically connected with one of the conductive members 102 b, and the second conductive pillar 103 b is disposed over and electrically connected with another one of the conductive members 102 b. In some embodiments, the second conductive pillar 103 b surrounds the first conductive pillar 103 a. In some embodiments, the first conductive pillar 103 a or the second conductive pillar 103 b is protruded from the RDL 102 and away from the substrate 101. In some embodiments, the first conductive pillar 103 a includes same material as or different material from the second conductive pillar 103 b. In some embodiments, the first conductive pillar 103 a has same configuration as the second conductive pillar 103 b. In some embodiments, the second conductive pillar 103 b has a height 112 substantially greater than a height H1 of the first conductive pillar 103 a. In some embodiments, a ratio of the height H1 to the height H2 is greater than about 1:1.5. In some embodiments, the second conductive pillar 103 b is disposed adjacent to an edge of the semiconductor structure 100. In some embodiments, the first conductive pillar 103 a is disposed at a central portion of the semiconductor structure 100.

in some embodiments, the first die 104 and the second die (105 or 106) are disposed over the substrate 101, the RDL 102 or the conductive pillars 103. In some embodiments, the first die 104 is electrically connected with at least one of the conductive pillars 103. In some embodiments, the first die 104 is disposed over the RDL 102 and electrically connected with the first conductive pillar 103 a. In some embodiments, the first die 104 is a small piece including semiconductive materials such as silicon, and is fabricated with a predetermined functional circuit within the first die 104 produced by photolithography operations. In some embodiments, the first die 104 is singulated from a silicon wafer by a mechanical or laser blade. In some embodiments, the first die 104 is a chip, a device or the like. In some embodiments, the first die 104 comprises a variety of electrical circuits suitable for a particular application. In some embodiments, the electrical circuits include various devices such as transistors, capacitors, resistors, diodes and/or the like. In some embodiments, the first die 104 has a top cross section (a cross section from a top view of the semiconductor structure 100) in a quadrilateral, a rectangular or a square shape.

In some embodiments, the first die 104 includes a first die substrate 104 a, a first side 104 b, a second side 104 c opposite to the first side 104 b and a first die pad 104 d disposed over the first side 104 b. In some embodiments, the first die substrate 104 a includes semiconductive material such as silicon or etc. In some embodiments, the first side 104 b is a front side or an active side of the first die 104. In some embodiments, the first side 104 b faces to the conductive pillars 103, the RDL 102 or the substrate 101. In some embodiments, the second side 104 c is a back side or an inactive side of the first die 104. In some embodiments, the first die pad 104 d includes conductive material such as copper, aluminum, gold or etc. In some embodiments, the first die pad 104 d is electrically connected with a circuitry of the first die substrate 104 a. In some embodiments, the first die pad 104 d is a conductive pillar protruded from the first side 104 b of the first die substrate 104 a. In some embodiments, the first die pad 104 d is in a cylindrical shape.

In some embodiments, the first die 104 is electrically connected with the first conductive pillar 103 a by a first conductive bump 107 a. In some embodiments, the first conductive bump 107 a is disposed between the first die 104 and the first conductive pillar 103 a. In some embodiments, the first die pad 104 d is electrically connected with the first conductive pillar 103 a by the first conductive bump 107 a. In some embodiments, the first conductive bump 107 a is in a cylindrical, hemispherical or spherical shape. In some embodiments, the first conductive bump 107 a is an electrical connector, a solder joint, a solder bump, a solder ball, a ball grid array (BGA) ball, controlled collapse chip connection (C4) bump, microbump, a pillar or the like or etc. In some embodiments, the first conductive bump 107 a includes conductive material such as includes solder, copper, nickel, gold or etc. In some embodiments, a soldering material is disposed between the first conductive pillar 103 a and the first conductive bump 107 a.

In some embodiments, the second die (105 or 106) is electrically connected with at least one of the conductive pillars 103. In some embodiments, the second die (105 or 106) is disposed over the RDL 102 and electrically connected with the second conductive pillar 103 b. In some embodiments, the second die (105 or 106) surrounds the first die 104. In some embodiments, the second die (105 or 106) is a small piece including semiconductive materials such as silicon, and is fabricated with a predetermined functional circuit within the second die (105 or 106) produced by photolithography operations. In some embodiments, the second die (105 or 106) is singulated from a silicon wafer by a mechanical or laser blade. In some embodiments, the second die (105 or 106) is a chip, a device or the like. In some embodiments, the second die (105 or 106) comprises a variety of electrical circuits suitable for a particular application. In some embodiments, the electrical circuits include various devices such as transistors, capacitors, resistors, diodes and/or the like. In some embodiments, the second die (105 or 106) has a top cross section (a cross section from a top view of the semiconductor structure 100) in a quadrilateral, a rectangular or a square shape. In some embodiments, the second die (105 or 106) is disposed more adjacent to an edge of the semiconductor structure 100 than the first die 104. In some embodiments, the second die (105 or 106) is disposed to surround the first die 104 from a top view perspective.

In some embodiments, the second die (105 or 106) includes a second die substrate (105 a or 106 a), a third side (105 b or 106 b), a fourth side (105 c or 106 c) opposite to the third side (105 b or 106 b) and a second die pad (105 d or 106 d) disposed over the third side (105 b or 106 b). In some embodiments, the second die substrate (105 a or 106 a) includes semiconductive material such as silicon or etc. In some embodiments, the third side (105 b or 106 b) is a front side or an active side of the second die (105 or 106). In some embodiments, the third side (105 b or 106 b) faces to the conductive pillars 103, the RDL 102 or the substrate 101. In some embodiments, the fourth side (105 c or 106 c) is a back side or an inactive side of the second die (105 or 106). In some embodiments, the second die pad (105 d or 106 d) includes conductive material such as copper, aluminum, gold or etc. In some embodiments, the second die pad (105 d or 106 d) is electrically connected with a circuitry of the second die substrate (105 a or 106 a). In some embodiments, the second die pad (105 d or 106 d) is a conductive pillar protruded from the third side (105 b or 106 b) of the second die substrate (105 a or 106 a). In some embodiments, the second die pad (105 d or 106 d) is in a cylindrical shape.

In some embodiments, the second die (105 or 106) is electrically connected with the second conductive pillar 103 b by a second conductive bump 107 b. In some embodiments, the second conductive bump 107 b is disposed between the second die (105 or 106) and the second conductive pillar 103 b. In some embodiments, the second die pad 105 d is electrically connected with the second conductive pillar 103 b by the second conductive bump 107 b.

In some embodiments, the second conductive bump 107 b is in a cylindrical, hemispherical or spherical shape. In some embodiments, the second conductive bump 107 b is an electrical connector, a solder joint, a solder bump, a solder ball, a ball grid array (BGA) ball, controlled collapse chip connection (C4) bump, microbump, a pillar or the like or etc. In some embodiments, the second conductive bump 107 b includes conductive material such as includes solder, copper, nickel, gold or etc. In some embodiments, a soldering material is disposed between the second conductive pillar 103 b and the second conductive bump 107 b.

In some embodiments, the dies (104, 105, 106, 111, or 112) have various thicknesses. The thicknesses of the dies (104, 105, 106, 111 or 112) are different from each other. In some embodiments, a thickness T1 of the first die 104 is substantially different from a thickness T2 of the second die (105 or 106). In some embodiments, the thickness T1 of the first die 104 is substantially greater than the thickness T2 of the second die (105 or 106).

In some embodiments, a distance between the second die (105 or 106) and the RDL 102 is substantially greater than a distance between the first die 104 and the RDL 102. In some embodiments, a distance D2 between the third side (105 b or 106 b) and the RDL 102 is substantially greater than a distance D1 between the first side 104 b and the RDL 102. In some embodiments, a total height of the first conductive pillar 103 a and the first die 104 is substantially same as a total height of the second conductive pillar 103 b and the second die 105. In some embodiments, a distance D3 between the second side 104 c and the RDL 102 is substantially same as a distance D4 between the fourth side 105 c and the RDL 102.

In some embodiments, the second side 104 c of the first die 104 and the fourth side (105 c or 106 c) of the second die (105 or 106) are at substantially same level. In some embodiments, the first side 104 b of the first die 104 is at a level substantially different from a level of the third side (105 b or 106 b) of the second die (105 or 106). In some embodiments, the second side 104 c of the first die 104 is horizontally aligned with the fourth side (105 c or 106 c) of the second die (105 or 106). Since the conductive pillars 103 have different heights, such heights difference can compensate different thicknesses between the first die 104 and the second die (105 or 106). As such, the thicknesses difference between the first die 104 and the second die (105 or 106) is balanced by the conductive pillars 103 in different heights. Thus, the second side 104 c of the first die 104 is at a level same as a level of the fourth side (105 c or 106 c) of the second die (105 or 106).

In some embodiments, dimensions of the dies (104, 105, 106, 111, 112) are different from each other. In some embodiments, a dimension of the first die 104 is substantially greater than a dimension of the second die (105 or 106). In some embodiments, as shown in FIG. 2, the dimension of the first die 104 is substantially greater than the dimension of the second die (105 or 106) and other dies (111 or 112). In some embodiments as shown in FIG. 2, a size of the first die substrate 104 a is substantially greater than a size of the second die substrate (105 a or 106 a). In some embodiments as shown in FIG. 2, a width of the first die substrate 104 a is substantially greater than a width of the second die substrate (105 a or 106 a).

FIG. 3 is a schematic cross sectional view of a semiconductor structure 200 in accordance with various embodiments of the present disclosure. In some embodiments, the semiconductor structure 200 is a semiconductor package. In some embodiments, the semiconductor structure 200 is a multiple dimensional package such as 2.5 dimensional package. In some embodiments, the semiconductor structure 200 includes a substrate 101, a redistribution layer (RDL) 102, several conductive pillars 103, several conductive bumps 107, a first die 104 and a second die (105 or 106), which have similar configurations as described above or as illustrated in FIG. 1 or 2.

In some embodiments, the semiconductor structure 200 includes an underfill material 108 disposed between the substrate 101 and the first die 104 or between the substrate 101 and the second die (105 or 106). In some embodiments, the underfill material 108 is disposed over the substrate 101 or the RDL 102. In some embodiments, the underfill material 108 fills gaps between the conductive pillars 103 or between the conductive bumps 107. In some embodiments, the underfill material 108 encapsulates the conductive pillars 103 or the conductive bumps 107. In some embodiments, the underfill material 108 contacts with the first side 104 b of the first die 104 or the third side (105 b or 106 b) of the second die (105 or 106). In some embodiments, the underfill material 108 protects the conductive pillars 103 or the conductive bumps 107 from moisture or other environmental hazards, and provides additional mechanical strength to the semiconductor structure 200. In some embodiments, the underfill material 108 covers a sidewall of the second die substrate (105 a or 106 a) of the second die (105 or 106) and contacts with the dielectric layer 102 a of the RDL 102. In some embodiments, the underfill material 108 includes epoxy, resin, polymer, etc.

In some embodiments, the semiconductor structure 200 includes a molding 109 surrounding the first die 104 and the second die (105 or 106). In some embodiments, the molding 109 is disposed over the substrate 101, the RDL 102 or the underfill material 108. In some embodiments, the molding 109 surrounds the underfill material 108. In some embodiments, the molding 109 encapsulates the underfill material 108, the first die 104, the second die (105 or 106), the conductive pillars 103 and the conductive bumps 107. In some embodiments, a portion of the molding 109 is disposed between the first die 104 and the second die (105 or 106). In some embodiments, the molding 109 is interfaced with the underfill material 108 and the sidewall of the second die (105 or 106). In some embodiments, the molding 109 is a single layer film or a composite stack. In some embodiments, the molding 109 includes various materials, such as molding compound, molding underfill, epoxy, resin, or the like. In some embodiments, the molding 109 has a high thermal conductivity, a low moisture absorption rate and a high flexural strength.

In some embodiments, a thickness of the molding 109 is substantially same as the distance D3 between the second side 104 c and the RDL 102 or the distance D4 between the fourth side (105 c or 106 c) and the RDL 102. In some embodiments, at least a portion of the first die 104 and at least a portion of the second die (105 or 106) are exposed from the molding 109. In some embodiments, the second side 104 c of the first die 104 and the fourth side (105 c or 106 c) of the second die (105 or 106) are exposed from the molding 109. In some embodiments, a top surface 109 a of the molding 109 is at a level substantially same as the level of the second side 104 c of the first die 104 or the level of the fourth side (105 c or 106 c) of the second die (105 or 106). In some embodiments, no molding 109 is disposed over the first die 104 or the second die (105 or 106), or the molding 109 does not cover the first die 104 or the second die (105 or 106). As such, the semiconductor structure 100 after thermal operations such as reflow operations would not be bended or curved. Therefore, warpage of the semiconductor structure 100 can be minimized or avoided. Furthermore, since the warpage of the semiconductor structure 100 is minimized or avoided, cold joint (i.e. some of the conductive bumps 107 are disposed away from or do not bond with the corresponding conductive pillars 103 due to the bending of the semiconductor structure 100) would be minimized or would not be present. As such, electrical connection between the conductive pillars 103 and the conductive bumps 107 are improved.

In some embodiments, the semiconductor structure 200 includes a heat dissipation means 110 such as heat sink, heat spreader or etc. disposed over the first die 104, the second die (105 or 106) and the molding 109. In some embodiments, the heat dissipation means 110 contacts with the first die 104 and the second die (105 or 106) in order to dissipate heat from the first die 104 or the second die (105 or 106). In some embodiments, the heat dissipation means 110 contacts with the second side 104 c of the first die 104 and the fourth side (105 c or 106 c) of the second die (105 or 106).

In some embodiments, a bond pad 101 d is disposed over or within the substrate 101. In some embodiments, the bond pad 101 d is disposed over the second surface 101 b of the substrate 101. In some embodiments, the bond pad 101 d includes conductive material copper, silver, nickel, aluminum, gold, titanium or tungsten, etc. In some embodiments, the bond pad 101 d is configured to receive a conductive structure.

In some embodiments, the substrate 101 includes a via 101 c extending through the substrate 101. In some embodiments, the via 101 c includes conductive material such as copper, silver, nickel, aluminum, gold, titanium or tungsten, etc. In some embodiments, the via 101 c is disposed between and electrically connected with the conductive member 102 b and the bond pad 101 d. In some embodiments, the via 101 c is electrically connected with the first die 104 or the second die (105 or 106) through the conductive bump 107, the conductive pillar 103 and the conductive member 102 b. In some embodiments, the via 101 c is a through silicon via (TSV).

In some embodiments, a connector 101 e is disposed over and electrically connected with the bond pad 101 d. In some embodiments, the connector 101 e is electrically connected with the via 101 c and the conductive member 102 b through the bond pad 101 d. In some embodiments, the connector 101 e is in a cylindrical, hemispherical or spherical shape. In some embodiments, the connector 101 e is a solder joint, a solder bump, a solder ball, a ball grid array (BGA) ball, controlled collapse chip connection (C4) bump, microbump, a pillar or the like or etc. In some embodiments, the connector 101 e includes conductive material such as includes solder, copper, nickel, gold or etc.

FIG. 4 is a schematic cross sectional view of a semiconductor structure 300 in accordance with various embodiments of the present disclosure. In some embodiments, the semiconductor structure 300 is a semiconductor package or an integrated circuit (IC) package. In some embodiments, the semiconductor structure 300 is a multiple dimensional package such as 2.5 dimensional package. In some embodiments, the semiconductor structure 300 includes a substrate 101, a redistribution layer (RDL) 102, several conductive pillars 103, several conductive bumps 107, a first die 104, a second die (105 or 106), a underfill material 108, a molding 109 and a heat dissipation means 110, which have similar configurations as described above or as illustrated in any one of FIGS. 1-3.

In some embodiments, the semiconductor structure 300 includes a board 301 and a pad 301 a disposed over the board 301. In some embodiments, the semiconductor structure 200 of FIG. 3 is disposed over the board 301 and bonded with the pad 301 a. In some embodiments, the board 301 includes semiconductive material such as silicon. In some embodiments, the board 301 is fabricated with a predetermined functional circuit. In some embodiments, the board 301 is a substrate, a device hoard, a printed circuit hoard (PCB), etc. In some embodiments, the pad 301 a includes conductive material such as copper, silver, nickel, aluminum, gold, titanium or tungsten, etc. In some embodiments, the pad 301 a is electrically connected with a circuitry of the board 301. In some embodiments, the pad 301 a is configured to receive a conductive structure. In some embodiments, the pad 301 a is electrically connected with and bonded with the connector 101 e. In some embodiments, the connector 101 e is disposed over the pad 301 a. In some embodiments, the board 301, the substrate 101, the first die 104 and the second die (105 or 106) are electrically connected through the conductive bump 107, the conductive pillar 103, the conductive member 102 b, the via 101 c, the bond pad 101 d and the connector 101 e.

In the present disclosure, a method of manufacturing a semiconductor structure (100, 200 or 300) is also disclosed. In some embodiments, a semiconductor structure (100, 200 or 300) is formed by a method 500. The method 500 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations. FIG. 5 is an embodiment of the method 500 of manufacturing a semiconductor structure (100, 200 or 300). The method 500 includes a number of operations (501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511 and 512).

In operation 501, a substrate 101 is provided or received as shown in FIG. 5A. In some embodiments, the substrate 101 is an interposer or a wafer. In some embodiments, the substrate 101 includes semiconductive material such as silicon. In some embodiments, the substrate 101 has similar configuration as described above or illustrated in any one of FIGS. 1-4. In some embodiments, the substrate 101 includes a RDL 102 disposed over the substrate 101. In some embodiments, the RDL 102 includes a dielectric layer 102 a disposed over the substrate 101 and a conductive member 102 b. In some embodiments, the dielectric layer 102 a is disposed by spin coating, deposition, chemical vapor deposition (CND) or any other suitable operations. In some embodiments, the conductive member 1028 is formed by sputtering, electroplating or any other suitable operations. In some embodiments, the substrate 101 includes a via 101 c and a bond pad 101 d. In some embodiments, the RDL 102, the dielectric layer 102 a, the conductive member 102 b, the via 101 c and the bond pad 101 d have similar configuration as described above or illustrated in any one of FIGS. 1-4.

In operation 502, a portion of the dielectric layer 102 a is removed as shown in FIG. 5B. In some embodiments, the portion of the dielectric layer 102 a is removed by any suitable operations such as etching operations, etc., such that a portion of a pad portion 102 b-1 of a conductive member 102 b of the RDL 102 is exposed. In some embodiments, a seed layer is disposed over the dielectric layer 102 a and the portion of the pad portion 102 b-1 exposed from the dielectric layer 102 a. In some embodiments, the seed layer is disposed between the dielectric layer 102 a and a first patterned mask 401. In some embodiments, the seed layer includes conductive material such as copper, titanium, etc.

In operation 503, a first patterned mask 401 is disposed over the RDL 102 as shown in FIG. 5C. In some embodiments, the first patterned mask 401 includes a first recess 401 a corresponding to the portion of the pad portion 102 b-1 exposed from the dielectric layer 102 a. In some embodiments, the first patterned mask 401 is formed by disposing a photoresist (PR) over the dielectric layer 102 a by deposition or any other suitable operations, and removing some portions of the PR by photolithography and etching operations to form the first recess 401 a.

In operation 504, a first conductive material is disposed over the RDL 102 exposed from the first patterned mask 401 to form a first conductive pillar 103 a as shown in FIG. 5D. In some embodiments, the first conductive material is disposed over the portion of the pad portion 102 b-1 exposed from the first patterned mask 401. In some embodiments, the first conductive material is disposed by electroplating or any other suitable operations. In some embodiments, the first conductive pillar 103 a is formed over the pad portion 102 b-1 and electrically connected with the conductive member 102 b. In some embodiments, a height of the first conductive pillar 103 a is substantially same as a thickness of the first patterned mask 401. In some embodiments, the first conductive pillar 103 a has similar configuration as described above or illustrated in any one of FIGS. 1-4.

In operation 505, the first patterned mask 401 is removed as shown in FIG. 5E. In some embodiments, the first patterned mask 401 is removed by etching, stripping or any other suitable operations. In some embodiments, a soldering material is disposed over the first conductive pillar 103 a.

In operation 506, a second patterned mask 402 is disposed over the RDL 102 as shown in FIG. 5F. In some embodiments, the second patterned mask 402 includes a second recess 402 a corresponding to a portion of the pad portion 102 b-1 exposed from the dielectric layer 102 a. In some embodiments, the second patterned mask 402 is formed by disposing a photoresist (PR) over the dielectric layer 102 a by deposition or any other suitable operations, and removing some portions of the PR by photolithography and etching operations to form the second recess 402 a. In some embodiments, a thickness of the second patterned mask 402 is substantially greater than a thickness of the first patterned mask 401.

In operation 507, a second conductive material is disposed over the RDL 102 exposed from the second patterned mask 402 to form a second conductive pillar 103 b as shown in FIG. 5G. In some embodiments, the second conductive material is disposed over the portion of the pad portion 102 b-1 exposed from the second patterned mask 402. In some embodiments, the second conductive material is disposed by electroplating or any other suitable operations. In some embodiments, the second conductive pillar 103 b is formed over the pad portion 102 b-1 and electrically connected with the conductive member 102 b. In some embodiments, a height of the second conductive pillar 103 b is substantially same as a thickness of the second patterned mask 402. In some embodiments, the height of the second conductive pillar 103 b is substantially greater than a height of the first conductive pillar 103 a. In some embodiments, the second conductive pillar 103 b has similar configuration as described above or illustrated in any one of FIGS. 1-4.

In operation 508, the second patterned mask 402 is removed as shown in FIG. 5H. In some embodiments, the second patterned mask 402 is removed by etching, stripping or any other suitable operations. In some embodiments, a soldering material is disposed over the second conductive pillar 103 b.

In operation 509, a first die 104 is disposed over the first conductive pillar 103 a as shown in FIG. 5I. In some embodiments, the first die 104 is bonded with the first conductive pillar 103 a by a first conductive bump 107 a. In some embodiments, the first conductive bump 107 a is formed by ball dropping, solder pasting or any other suitable operations. In some embodiments, the first die 104 and the first conductive bump 107 a have similar configuration as described above or illustrated in any one of FIGS. 1-4.

In operation 510, a second die (105 or 106) is disposed over the second conductive pillar 103 b as shown in FIG. 5J. In some embodiments, the second die (105 or 106) is bonded with the second conductive pillar 103 b by a second conductive bump 107 b. In some embodiments, the second conductive bump 107 b is formed by ball dropping, solder pasting or any other suitable operations. In some embodiments, a second side 104 c of the first die 104 is at a level substantially same as a level of a fourth side (105 c or 106 c) of the second die (105 or 106). In some embodiments, the second die (105 or 106) and the second conductive bump 107 b have similar configuration as described above or illustrated in any one of FIGS. 1-4. In some embodiments, a semiconductor structure 100 is formed which has similar configuration as illustrated in FIG. 1.

In operation 511, an underfill material 108 is disposed over the substrate 101 as shown in FIG. 5K. In some embodiments, the underfill material 108 encapsulates the first conductive pillar 103 a, the second conductive pillar 103 b, the first conductive bump 107 a and the second conductive bump 107 b. In some embodiments, the underfill material 108 has similar configuration as described above or illustrated in any one of FIGS. 1-4.

In operation 512, a molding 109 is disposed over the substrate 101 as shown in FIG. 5L. In some embodiments, the molding 109 surrounds the underfill material 108, the first die 104 and the second die (105 or 106). In some embodiments, the molding 109 is formed by disposing a molding material such as molding compound, epoxy or etc. over the underfill material 108 and the substrate 101. In some embodiments, the molding 109 is disposed by transfer molding, compression molding or any other suitable operations. In some embodiments, the second side 104 c of the first die 104 and the fourth side (105 c or 106 c) of the second die (105 or 106) are exposed from the molding 109. In some embodiments, a top surface 109 a of the molding 109 is at a level substantially same as a level of the second side 104 c of the first die 104 and a level of the fourth side (105 c or 106 c) of the second die (105 or 106). In some embodiments, the molding 109 has similar configuration as described above or illustrated in any one of FIGS. 1-4.

In some embodiments as shown in FIG. 5M, a heat dissipation means 110 is disposed over the first die 104 and the second die (105 or 106). In some embodiments, a connector 101 e is disposed over the bond pad 101 d of the substrate 101. In some embodiments, the connector 101 e is formed by ball dropping, solder pasting or any other suitable operations. In some embodiments, the heat dissipation means 110 and the connector 101 e have similar configuration as described above or illustrated in FIG. 3 or 4. In some embodiments, a semiconductor structure 200 is formed as illustrated in FIG. 3.

In some embodiments as shown in FIG. 5N, a board 301 including a pad 301 a is provided or received. In some embodiments, the connector 101 e is bonded with the pad 301 a. In some embodiments, the board 301 and the pad 301 a have similar configuration as described above or illustrated in FIG. 4. In some embodiments, a semiconductor structure 400 is formed as illustrated in FIG. 4.

A semiconductor structure is disclosed. The semiconductor structure includes dies in various thicknesses and conductive pillars in various heights correspondingly. As such, the thickness difference between the dies would be compensated by the conductive pillars in different heights, and the backsides of the dies would be disposed at a level same as each other. Since no molding is present over the backsides of the dies, the warpage of the semiconductor structure after thermal operations would be prevented or minimized, and cold joint would be avoided.

In the present disclosure, a method of manufacturing a semiconductor structure is disclosed. The method includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar and a third conductive pillar are disposed over the substrate. The first conductive pillar comprises a first height, the second conductive pillar comprises a second height, and the third conductive pillar comprises a third height different from the first height and the second height. A first die is disposed over the first conductive pillar. The first die comprises a first surface distal to the substrate. A second die is disposed over the second conductive pillar. The second die comprises a second surface distal to the substrate. The first surface of the first die and the second surface of the second die are at substantially same level.

In some embodiments, a method of manufacturing a semiconductor structure is disclosed. The method includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar and a third conductive pillar are disposed over the substrate. The third conductive pillar comprises a third height different from a first height of the first conductive pillar and a second height of the second conductive pillar. A first die is disposed over the first conductive pillar and a second die is disposed over the second conductive pillar. A height of the first die is different from a height of the second die. An inactive side of the first die is horizontally aligned with an inactive side of the second die.

In some embodiments, a method of manufacturing a semiconductor structure is disclosed. The method includes the following operations. A substrate is provided. The substrate includes a redistribution layer (RDL) disposed over the substrate. A first conductive pillar, a second conductive pillar and a third conductive pillar are disposed over the substrate. A first die is disposed over the first conductive pillar. A second die is disposed over the second conductive pillar. A third die is disposed over the third conductive pillar. A third height of the third conductive pillar is different from a first height of the first conductive pillar and a second height of the second conductive pillar, and a first surface of the first die, a second surface of the second die and a third surface of the third die are at substantially same level.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A method of manufacturing a semiconductor structure, comprising: providing a substrate; disposing a first conductive pillar, a second conductive pillar and a third conductive pillar over the substrate, the first conductive pillar comprising a first height, the second conductive pillar comprising a second height, and the third conductive pillar comprising a third height different from the first height and the second height; disposing a first die over the first conductive pillar, the first die comprising a first surface distal to the substrate; and disposing a second die over the second conductive pillar, the second die comprising a second surface distal to the substrate, wherein the first surface of the first die and the second surface of the second die are at substantially same level.
 2. The method of claim 1, wherein the substrate further comprises a redistribution layer (RDL) disposed over the substrate.
 3. The method of claim 2, wherein a distance between the first surface of the first die and the RDL is substantially same as a distance between the second surface of the second die and the RDL.
 4. The method of claim 1, wherein the substrate further comprises a via extending through the substrate.
 5. The method of claim 1, further comprising disposing an underfill material over the substrate, and the underfill material encapsulating the first conductive pillar, the second conductive pillar, and the third conductive pillar.
 6. The method of claim 1, further comprising disposing a third die over the third conductive pillar.
 7. The method of claim 6, wherein the first die comprises a first thickness, the second die comprises a second thickness, and the third die comprises a third thickness different from the first thickness and the second thickness.
 8. The method of claim 1, further comprising bonding the first die with the first conductive pillar by a first conductive bump.
 9. The method of claim 1, further comprising disposing a molding over the substrate.
 10. The method of claim 9, wherein a surface of the molding and the first surface of the first die are at substantially same level.
 11. The method of claim 9, further comprising disposing a heat dissipation means over the molding.
 12. The method of claim 11, wherein a distance between the first conductive pillar and the heat dissipation means is greater than a distance between the second conductive pillar and the heat dissipation means.
 13. A method of manufacturing a semiconductor structure, comprising: providing a substrate; disposing a first conductive pillar, a second conductive pillar and a third conductive pillar over the substrate, the third conductive pillar comprising a third height different from a first height of the first conductive pillar and a second height of the second conductive pillar; and disposing a first die over the first conductive pillar and disposing a second die over the second conductive pillar, wherein a height of the first die is different from a height of the second die, and an inactive side of the first die is horizontally aligned with an inactive side of the second die.
 14. The method of claim 13, further comprising disposing a third die over the third conductive pillar.
 15. The method of claim 14, wherein a total height of the first conductive pillar and the first die is substantially same as a total height of the third conductive pillar and the third die.
 16. A method of manufacturing a semiconductor structure, comprising: providing a substrate including a redistribution layer (RDL) disposed over the substrate; disposing a first conductive pillar, a second conductive pillar and a third conductive pillar over the substrate; disposing a first die over the first conductive pillar; disposing a second die over the second conductive pillar; and disposing a third die over the third conductive pillar, wherein a third height of the third conductive pillar is different from a first height of the first conductive pillar and a second height of the second conductive pillar, and a first surface of the first die, a second surface of the second die and a third surface of the third die are at substantially same level.
 17. The method of claim 16, wherein the disposing the first conductive pillar further comprises: disposing a first patterned mask over the RDL, the first patterned mask exposing at least a conductive member; and disposing a first conductive material over the conductive member exposed from the first patterned mask to form the first conductive pillar.
 18. The method of claim 17, wherein the disposing the second conductive pillar further comprises: disposing a second patterned mask over the RDL the second patterned mask exposing at east a conductive member; and disposing a second conductive material over the conductive member exposed from the second patterned mask to form the second conductive pillar.
 19. The method of claim 18, wherein a thickness of the second patterned mask is substantially greater than a thickness of the first patterned mask.
 20. The method of claim 18, further comprising: disposing a seed layer between the RDL and the first patterned mask or between the RDL and the second patterned mask. 